(1) Field of the Invention
The present invention relates to a method and apparatus for minimizing the effects of defects in an integrated circuit chip. More specifically, the present invention controls the initialization of shifters with a shift pattern for column redundancy in highly parallel memory structures such as the multiple banks of a cache memory on a microprocessor integrated circuit chip.
(2) Prior Art
It is quite common for a fast central processor unit to feature parallel data paths such as a 32 bit or a 64 bit bus for transferring data into and out of its memory storage. Likewise, most memory storage comprises semi-conductor memories organized in rectangular arrays of rows and columns on very-large-scale integrated (VLSI) circuits. The intersection of one row and one column results in a storage element called a "cell". Each cell is capable of storing a binary bit of data. To write data into, and to read data from, a row or column of cells, an address is assigned to each row or column of cells. Access to the address is provided by a binary coded address presented as input to address decoders that select a row or column for a write or read operation. As semiconductor memories become more and more dense, the arrays of cells become more and more susceptible to the presence of defects which could impede or corrupt the flow of data through any of the desired paths.
Defects in semi-conductor memories occur during the fabrication of an integrated circuit. Under the rubric of defects, one may include wafer defects, oxide defects, metallization defects, interconnect defects, contamination defects, unintended or missing connections, missing or extra contacts and others. To avoid unnecessarily confusing the presentation of the invention, an "open" defect refers to a defect affecting the data path for one bit of data, while a "short" defect refers to a defect affecting the paths of more than one bit of data (typically adjacent bits).
On-chip redundancy is the construction of redundant elements on an integrated chip to bypass the data paths affected by the defects while preserving the original addresses of the affected data paths. For example, if the chip contains a memory array, redundant elements are provided. Thus, if a defect in one or more primary data elements is detected, the redundant elements can be switched into use in place of the defective primary element or elements.
In the past, on-chip redundancy was implemented with latches or laser zappable fuses located on each column or row of data path. Latches are volatile and require that the information identifying the cells affected by defects be stored externally to the semi-conductor memory, for example, on a disk, so that when power is turned on, the entire system does not have to be retested for defects. The fuses are used to resolve a defect or error found in the original data elements such that signals are shifted to use the redundant data elements, thereby avoiding the defective elements.
Laser zappable fuses are physically implemented in CMOS circuits in one of two ways. If the fuse is "normally closed," it is usually made with a polysilicon fuse which can be opened by selective laser zapping. If the fuse is "normally open," it is usually made with a NMOS or a PMOS transistor whose gate voltage is controlled by "normally closed" laser zappable fuses.
The use of latches or laser zappable fuses on each column or row of data path imposes technology constraints. In particularly, to avoid damage to surrounding circuitry when a fuse is "zapped," considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The additional area required for the fuses is generally contradictory with the tight spacing requirements inherent in memory arrays.
As applicable to wide-word computing such as the popular use of 32-bit or 64-bit data paths, a number of additional problems arise. A single redundant set of arrays cannot compensate for a short defect between arrays belonging to two adjacent sets. Therefore, at least two sets would be needed to correct such defects. Additionally, data transmissions along the redundant path can suffer a speed penalty due to the extra line length and the incidence of higher parasitic capacitance. In some instances, the input and output data path may be tripled in length for a wide-word computing device. Variable delays from data paths are highly undesirable in high-performance memory storage, as they force the performance of an entire memory array to be no better than that of the extended length path's performance. Finally, fuses must be laid out integrally to each set so as to be able to selectively disconnect sets in which defects exist.
An apparatus and method for switching the arrays of parallel data paths in memory data structures upon the detection of defects in the data path or memory storage device is disclosed in co-pending U.S. patent application Ser. No. 07/605,510, entitled "Method and Apparatus for Implementing Redundancy in Parallel Memory Structures" which was filed on Oct. 30, 1990 and is hereby incorporated fully by reference. Prior to the invention of the co-pending application, redundancy had been implemented using duplicate arrays connected to laser zappable fuses. The use of laser fuses imposes restrictive technology constraints. In particular, to avoid damage to surrounding circuitry when a fuse is "zapped," considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The co-pending application uses only two extra parallel arrays to correct for any open or short defects in a parallel memory data structure, and it makes the correction with nearly constant array lengths which are about the same as the original arrays. The redundancy arrays as well as the original arrays are connected to toggle switches. Upon encountering any open or short in the one or more data paths, the toggle switches coupled to the data paths affected by the open or short are "flipped" to connect to the adjacent data paths in a cascading fashion. The toggle switches are implemented with NMOS or PMOS transistors in a CMOS array. It follows that the co-pending application invention obviates having a latch or laser zappable fuse on each column or row of data path. The toggle switches are controlled with a pointer register which can be implemented either by logically decoding the defect area or by actually implementing a shifter which stops when its state reaches the defect.
As microprocessors become more and more sophisticated, and as the die sizes grow, it is common for a microprocessor integrated circuit chip to include several memory arrays (e.g. cache memories, translation look-aside buffers) on the integrated circuit chip. It is also common for an individual cache memory to be divided into several banks of highly parallel memory structures. While the teachings of the co-pending invention could be used to repair defects in banks of on-board cache memory simply by duplicating the shifter such that there is one independent control for each shifter, there would be much duplication of logic. The present invention provides a method and apparatus for controlling the initialization of many shifters while minimizing the duplication of logic.